Electronic systems comprise, among other things, a plurality of printed circuit boards with electronic components. Such components may be application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), dynamic random access memories (DRAMs), flash memories, central processing units (CPUs), read only memories (ROMs), capacitors, inductors, resistors and wires. With the improvement of semiconductor technology, most of chip to chip and board to board electronic interfacing occurs through the use of a serializer and deserializer (serdes) protocol, over which transaction level communication occurs. When the semiconductor technology was not fully matured, the speeds achievable at these serdes interfaces were limited. Accordingly, pin count optimization was not possible through use of serdes technology as the low speeds limited the bandwidth of communication. Such limitation in bandwidth was compensated through widening of the chip-to-chip and board-to-board interfaces from being a single data bit interface to a byte (8 bits), half word (16 bits), word (32 bits) or double word (64 bits).
Serial interconnects have matured to the point where speed, reliability, and robustness make them a viable option for board-to-board connections. By eliminating need for parallel busses and defining new protocols leveraging serial technologies such as PCI Express, Ethernet, Serial RapidIO, pins can be freed up to support proper number of data and control plane pins without losing board-to-board bandwidth.
The original version of VME created in the 1980 and standardized as IEEE 1014-1987, called for 3U and 6U form factors for the backplanes. The 3U format comprises of a single 96-pin P1 connector to support the popular 16-bit microprocessors and the board size was similar to contemporary standards.
However, over time the 3U VME format lost its place as address and data bus widths increased, calling for more pins on the backplane. As 32-bit processors evolved, the 6U format with both P1 and P2 connectors became the de facto size of choice for VME.
The 3U and 6U form factors are also chosen for VPX, the ANSI/VITA 46 family of specifications. VPX has defined both a 3U and 6U format, allowing designers to choose the best for their application. VPX is an ANSI standard (ANSI/VITA 46.0-2007) that provides VME bus-based systems with support for switched fabrics over a new high speed connector. A 3U front panel is 132 mm long, while a 6U front panel is 265 mm long, and both are 100 mm in width.
New generations of embedded computing systems based on the VPX standard reflect the growing significance of high speed serial switched fabric interconnects such as RapidIO, 10 Gigabit Ethernet, PCI Express, and Infiniband. These technologies are replacing traditional parallel communications bus architectures for local communications, because they offer significantly greater capability. Switched fabrics technology supports multiprocessing systems that require the faster possible communications between processors (e.g., digital signal processing applications). VPX gives the large existing base of VMEbus users access to these switched fabrics. Technologies called for in VPX include 3U and 6U formats and new 7-row high speed connector rated up to 6.25 Gbit/s. In networking applications, these speeds are now approaching 25 Gbit/s.
As a drawback, increase of width of the interfaces has a consequent cost component as the increase in pin count mandated a costlier chip package, larger PCBs, higher power dissipation. With advent of higher integration and improvements in semiconductor technology, the clock speed of a serdes interface, which was limiting, increased exponentially. Where a serdes interface of 550 MHz at one point was a challenge, current serdes technology is now feasible to support upto 25 Gbit/s. With this exponential improvement in speed, the widening of the bus width to meet bandwidth requirements is no longer needed. Semiconductor chips and PCB designers exploited this improvement in technology to design inter-chip and inter-board protocols with serdes interfaces. While enabling more integration and reduction of sizes of the PCBs and semiconductor chips, the high speed interfaces between chips and between boards over backplanes have to be robustly designed for the protocols over them to work correctly.
The serdes interfaces between boards and chips over the backplanes, operating at very high speeds have to be tested for feasibility and reliability of correct bit transfer at desired rates. Tests have to be run and interfaces characterized and measured for best and worst case transition delay, temperature and process variations. Such measurements require a minimum of two and up to supportable slots of PCBs to be populated over a backplane. Then signals over and between any two slots are to be measured and characterized for these parameters. In the current state of technology, such measurements require human intervention, design of daughter cards, soldering and connecting probes and wires on boards under test. At very high speeds, such efforts affect both geometry and physical behavior of the electrical circuit that is subject of test and characterization. Accurate measurements are difficult due to fringe effects, hard to maintain uniformity and variations due to human touch. Due to abrupt and numerous connections and disconnections, a likelihood of damage to the semiconductor component or the PCB is not ruled out. Sometimes this leads to discard of entire PCB due to failure of a single semiconductor component. Losses this way affect the margins and increase the recurring costs in product design.
The present invention overcomes these challenges in backplane design, test and characterization. A probe card is designed, which is connectable in slot increments in one dimension and in pin pitch increment in other dimension on the backplane interconnects of the PCB. Two probe cards, located in different slots of the backplane are required to check the electrical performance of traces routed on the backplane. The probe cards have to be moved and positioned in increments relating to the slot to slot pitch and to the backplane connector's own row to row pitch.
The probe card provides mechanics to be able to engage and disengage the connections, avoiding need of human intervention on the PCBs. The probe card, designed as a semi-circle in one embodiment, provides the probe connects distributed along its circumference for easy connections to probes, drivers and receivers of the serial or parallel connections. In the present invention, test, diagnosis, probing and characterization are enabled while overcoming the shortcomings of the present art. Reliability, cost, time to design and market are all positively impacted.
Conventional probe cards are generally inserted into the backplane without any mechanical features guiding the process. Probe cards equipped with connectors with high insertion forces, like Multi-Gig connectors, are difficult to position and connect/disconnect from the backplane without damaging the connectors or without affecting the accuracy of the backplane performance measurements. The present invention overcomes these shortcomings.
Due to this invention, both testing and qualification of electrical interface is facilitated by providing symmetric, robust and functionally isolated probing points for backplane signals. The method and apparatus is flexible and adaptive to all laboratory test assemblies and equipment. Measurements are accurate and effect of human interventions in making and changing connections in the laboratory are minimized and isolated from probing results. Damages to sensitive electronic parts and components are minimized.